1. Field of the Invention
This invention relates to a wafer and a method for manufacturing the same.
2. Background Art
Transistors such as IGBT (insulated gate bipolar transistor) and power MOSFET (metal oxide semiconductor field effect transistor) are used in high-power switching circuits. In these transistors, the operating current flows vertically to the substrate. Hence, thinning the device thickness to reduce series resistance leads to reduced on-resistance during operation, allowing low power consumption.
On the other hand, wafer diameter is being increased to reduce the cost of semiconductor devices.
However, a wafer with a larger diameter is more susceptible to cracking, warpage, and chipping when it is thinned. This increases the ineffective region of the wafer and decreases the number of non-defective devices. A thick flange at the wafer periphery is an effective structure for preventing cracking, warpage, and chipping of the wafer while thinning the wafer to reduce series resistance.
With regard to a silicon wafer and a method for manufacturing the same, JP-A-2000-260670(Kokai) discloses a technique for reducing the wafer thickness without substantially decreasing the mechanical strength. In this technique, a recess is formed throughout one side or both sides of the silicon wafer excluding at least the wafer periphery. However, forming a flange causes a problem of increasing the ineffective region of the wafer.